A wide variety of integrated circuit memories are available for storing data. One type of memory is the dynamic random access memory (DRAM). A DRAM is designed to store data in memory cells formed as capacitors. The data is stored in a binary format; for example a logical "one" can be stored as a charge on a capacitor, and a logical "zero" can be stored as a discharged capacitor. The typical DRAM has memory cells arranged in addressable rows and columns. To access a memory cell, a row is first addressed so that all memory cells coupled with that row are available for accessing. After a row has been addressed, at least one column can be addressed to pinpoint at least one specific memory cell for either data input or output. The data stored in the memory cells is, therefore, accessible via the columns.
With the constant development of faster computer and communication applications, the data rates in which a memory circuit must operate continue to increase. To address the need for increased data rates, a variety of DRAMs are commercially available. These memories are produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells of the memory. One such method is page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell array and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode DRAMs require access steps which limit the communication speed of the memory circuit.
An alternate type of memory circuit is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory circuit can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on the communication lines. Column access times are, therefore, "masked" by providing the extended data output. A more detailed description of a DRAM having EDO features is provided in the "1995 DRAM Data Book" pages 1-1 to 1-30 available from Micron Technology, Inc. Boise, Id., which is incorporated herein by reference.
Yet another type of memory device is a burst EDO memory which adds the ability to address one column of a memory array and then automatically address additional columns in a pre-determined manner without providing the additional column addresses on external address lines. These memory devices use a column address input to access the memory array columns.
Integrated memory devices often require relatively large currents during active operation and much lower currents during inactive modes. With the increases being achieved in memory density and the increased number of memories being incorporated into systems, such as personal computer systems, the power supply current requirements of individual memories must be carefully controlled. Thus, some random access memory devices (RAMs) have a standby mode which regulates the internal power supply to reduce power consumption when the memories are in an inactive state. These RAMs use the row address strobe signal (RAS.sup.*) signal as a control for the internal regulator circuitry. This creates problems with RAMs which can operate in an active mode after a .sup.* RAS cycle has ended.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for memory devices which regulate internal power supplies to reduce current demands while reducing electrical noise experienced during memory operation.